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CCD201-20 back illuminated 2-phase imo series electron multiplying ccd sensor introduction the ccd201 is a large format sensor ( 4 1k 2 ) in the l3vision tm range of products from e2v technologies. this device uses a novel output amplifier circuit that is capable of operating at an equivalent output noise of less than one electron at pixel rates of over 15 mhz. this makes the sensor well suited for scientific imaging where the illumination is limited. the sensor is a frame transfer device and can operate in inverted mode to suppress dark current as this is now the dominant noise source (even at high readout rate). the image and store sections are designed to operate in 2-phase mode, to maximise the highest achievable parallel transfer frequency. the sensor functions by converting photons to charge in the image area during the integration time period, then transferring this charge through the image and store sections into the readout register. following transfer through the readout register, the charge is multiplied in the gain register before conversion to a voltage by an output amplifier. the sensor has two output amplifiers; a low noise, high responsivity output for normal ccd operation and a large signal amplifier for when multiplication gain is employed. operation of the high gain mode is controlled by adjustment of the multiplication phase amplitude r 1 2hv. general data active image area ......... 13.3 x 13.3 mm image section active pixels ..... 1024 (h) x 1024 (v) image pixel size ............13x13 m m number of output amplifiers .......... 2 fill factor ............... 100% additional dark reference columns ....... 32 additional overscan rows ........... 8 package details (see fig. 15) ceramic package overall dimensions ......... 37.4 x 26.5 mm number of pins .............. 36 inter-pin spacing ........... 2.54 mm mounting position ............. any the pin 1 marker is shown in fig. 15. storage and operation temperature extremes min max storage temperature ( 8 c) 7 200 +100 operating temperature ( 8 c) 7 120 +75 temperature ramping ( 8 c/min) C 5 note: operation or storage in humid conditions may give rise to moisture on the sensor surface on cooling, causing irreversible damage. # e2v technologies (uk) limited 2005 a1a-100013 issue 1, june 2005 411/9140 e2v technologies (uk) limited, waterhouse lane, chelmsford, essex cm1 2qu, uk telephone: +44 (0)1245 493493 facsimile: +44 (0)1245 492492 e-mail: enquiries@e2v.com internet: www.e2v.com holding company: e2v technologies plc e2v technologies inc. 4 westchester plaza, po box 1482, elmsford, ny10523-1482 usa telephone: (914) 592-6050 facsimile: (914) 592-5148 e-mail: enquiries@e2vtechnologies.us
typical performance specifications except where otherwise specified, the following are measured for operation at a pixel rate of 15 mhz, with typical operating voltages. parameters are given at 223 k unless specified otherwise. where parameters are different in the normal and high gain mode, both are given. parameter unit min typical max output amplifier responsivity, hr amplifier (normal mode) (see note 1) m v/e 7 C 5.3 C output amplifier responsivity, ls amplifier (normal mode) (see note 1) m v/e 7 C 1.4 C multiplication register gain, ls amplifier (high gain mode) (see notes 2, 3 and 4) 1 C 1000 peak signal - 2-phase imo e 7 /pixel 50k 80k C charge handling capacity of multiplication register (see note 5) e 7 /pixel C 730k C charge handling capacity of hr amplifier (see note 6) e 7 C 280k C charge handling capacity of ls amplifier (see note 6) e 7 C1mC readout noise at 50 khz with cds, hr amplifier (normal mode) (see note 6) e 7 rms C 3.1 C readout noise at 1 mhz with cds, hr amplifier (normal mode) (see note 6) e 7 rms C 6.0 C amplifier reset noise (without cds), hr amplifier (normal mode) (see note 6) e 7 rms C 50 C readout noise at 15 mhz with cds, ls amplifier (normal mode) (see note 6) e 7 rms C 43 C amplifier reset noise (without cds), ls amplifier (normal mode) (see note 6) e 7 rms C 100 C readout noise at 1 mhz (high gain mode) (see note 6) e 7 rms C 5 1C maximum frequency (settling to 1%), hr amplifier (see notes 6 and 7) mhz C C 3 maximum frequency (settling to 5%), hr amplifier (see notes 6 and 7) mhz C C 4.5 maximum frequency (settling to 1%), ls amplifier (see note 6 and 7) mhz C C 13 maximum frequency (settling to 5%), ls amplifier (see note 6 and 7) mhz C C 20 maximum parallel transfer frequency (see note 1) mhz C 0.9 C dark signal at 293 k (see note 8) e 7 /pixel/s C 260 530 dark signal non-uniformity (dsnu) at 293 k (see note 9) e 7 /pixel/s C 90 C excess noise factor (see note 10) C h 2C notes 1. measured at a pixel rate of 1 mhz. 2. the typical variation of gain with r 1 2hv is shown in fig. 1. 3. the variation of gain with r 1 2hv at different temperatures is shown in fig. 1. 4. some increase of r 1 2hv may be required throughout life to maintain gain performance. adjustment of r 1 2hv should be limited to the maximum specified under operating conditions. 5. when multiplication gain is used and clock timings optimised, a linear response of output signal with input signal of better than 3% is achieved for output signals up to 400 ke 7 typically. 6. these values are inferred by design and not measured. 7. the quoted maximum frequencies assume a 20 pf load and that correlated double sampling is being implemented. 8. the quoted dark signal has the usual temperature dependence for inverted mode operation. for operation at high frame rates with short integration times, there will also be a component generated during readout through the register. operating at a temperature of 293 k and 10 hz frame rate, the readout component contributes 5.8 e 7 /pixel/frame typically, at a gain of 1000 and referenced to the image area, and has a temperature dependence consistent with non-inverted mode operation. there exists a further weakly temperature dependent component, the clock induced charge, which is independent of the integration time. the clock induced charge is dependent on the operating biases and timings employed and is typically 0.2 e 7 / pixel/frame at t = 7 55 8 c. for more information, refer to the technical note "dark signal and clock-induced charge in l3vision tm ccd sensors". 9. dsnu is defined as the 1 s variation of the dark signal. 10. the excess noise factor is defined as the factor by which the multiplication process increases the shot noise on the image when multiplication gain is used. 100013, page 2 # e2v technologies
device cosmetic performance grade 1 devices are supplied to the blemish specification shown below. note that incorrect biasing of the device may result in spurious dark or white blemishes appearing. these will be eliminated if the biases are adjusted. test conditions operating mode devices run in 2-phase inverted mode, with an integration time of 100 ms and a readout rate of 15 mhz. sensor temperature 18 + 3 8 c. multiplication gain set to approximately 1000. illumination set to give a signal level of approximately 60 e 7 /pixel/frame. blemish specification black columns black defects are counted when they have a responsivity of less than 80% of the local mean signal at approximately the specified multiplication gain and level of illumination. a black column contains at least 9 contiguous black defects. white columns white defects are pixels having a dark signal generation rate corresponding to an output signal of greater than 5 times the maximum specified dark signal level. a white column contains at least 9 contiguous white defects. pin-head columns pin-head columns are manifest as a partial dark column with a bright pixel showing photoresponse at the end of the column nearest to the readout register. pin-head columns are counted when the black column has a responsivity of less than 80% of the local mean signal at approximately the specified multiplication gain and level of illumination. a pin-head column contains at least 9 contiguous black defects. specification parameter grade 1 specification grade 2 specification white columns 0 0 black /pin-head columns 1 6 ordering information part number operating mode coating window CCD201-20-*- 122 2-phase midband temporary * denotes grade of device. # e2v technologies 100013, page 3
1000 100 10 1 39 40 41 42 43 44 45 46 r 1 2hv (v) multiplication gain t = 293 k t = 273 k t = 253 k t = 233 k t = 223 k 8284 figure 1: typical variation of multiplication gain with r 1 2hv at different temperatures figure 2: typical variation of dark signal with temperature 100013, page 4 # e2v technologies 10 7 1 10 7 2 1 10 10 2 10 3 10 4 dark signal (e 7 /pixel/s) sensor temperature ( 8 c) 7 40 7 20 0 20 40 8299
100 90 80 70 60 50 40 30 20 10 0 300 400 500 600 700 800 900 1000 wavelength (nm) quantum efficiency (%) 8216 figure 3: typical spectral response (at 7 20 8 c, no window, midband coating) # e2v technologies 100013, page 5 esd handling procedures ccd sensors, in common with most high performance ic devices, are static sensitive. in certain cases a static electricity discharge may destroy or irreversibly degrade the device. accordingly, full anti-static handling precautions should be taken whenever using a ccd sensor or module. these include: * working at a fully grounded workbench. * operator wearing a grounded wrist strap. * all receiving socket pins to be positively grounded. * unattended ccds should not be left out of their conducting foam or socket. all devices are provided with internal protection circuits to most gate electrodes but not to the other pins. evidence of incorrect handling will terminate the warranty. exposure to radiation exposure to radiation may irreversibly damage the device and result in degradation of performance. users wishing to operate the device in a radiation environment are advised to consult e2v technologies.
absolute maximum ratings maximum ratings are with respect to ss. pin connection description min (v) max (v) 1 abd anti-blooming drain (see note 11) 7 0.3 +25 2 ss substrate 0 3i 1 4 image clock 4 7 20 +20 4i 1 3 image clock 3 7 20 +20 5s 1 4 store clock 4 7 20 +20 6s 1 2 store clock 2 7 20 +20 7 ss substrate 0 8 ss substrate 0 9 dg dump gate 7 20 +20 10 og output gate 7 20 +20 11 odh output drain (hr amplifier) 7 0.3 +32 12 rd reset drain 7 0.3 +25 13 odl output drain (ls amplifier) 7 0.3 +32 14 ss substrate 0 15 osh output source (hr amplifier) (see note 12) 7 0.3 +25 16 osl output source (ls amplifier) (see note 12) 7 0.3 +25 17 1 r reset pulse 7 20 +20 18 r 1 dc multiplication register dc bias 7 20 +20 19 r 1 2hv multiplication register clock 7 20 +50 20 dg dump gate 7 20 +20 21 n.c. not connected 22 n.c. not connected 23 ss substrate 0 24 n.c. not connected 25 n.c. not connected 26 dd dump drain 7 0.3 +25 27 r 1 3 register clock 3 7 20 +20 28 r 1 1 register clock 1 7 20 +20 29 r 1 2 register clock 2 7 20 +20 30 ss substrate 0 31 s 1 3 store clock 3 7 20 +20 32 s 1 1 store clock 1 7 20 +20 33 i 1 1 image clock 1 7 20 +20 34 i 1 2 image clock 2 7 20 +20 35 ss substrate 0 36 ig isolation gate 7 20 +20 notes 11. anti-blooming is not available on this device type. however, abd is used for connection purposes and must be biased as specified. 12. permanent damage may result if, in operation, osl or osh experience short-circuit conditions. 100013, page 6 # e2v technologies
operating conditions typical operating voltages are as given in the table below. some adjustment within the minimum-maximum range specified may be required to optimise performance. connection pulse amplitude or dc level (v) min typical max i 1 1,2,3,4 high +5 (see note 13) +7 +9 (see note 13) i 1 1,2,3,4 low 7 6 7 5 7 4 s 1 1,2,3,4 high +5 (see note 13) +7 +9 (see note 13) s 1 1,2,3,4 low 7 6 7 5 7 4 r 1 1,2,3 high +8 +12 +13 r 1 1,2,3 low C 0 C r 1 2hv high +20 +40 +50 (see note 4) r 1 2hv low 0 +4 +5 1 r high see note 14 +10 see note 14 1 r low C 0 C r 1 dc +2 +3 +5 og +1 +3 +5 ig C 7 5C ss 0 +4.5 +7 odl, odh +25 +28 +32 rd +15 +17 +20 abd +10 +18 +20 dg low C 0 C dg high +10 +12 +13 dd +20 +24 +25 notes 13. i 1 and s 1 adjustment may be common. 14. 1 r high level may be adjusted in common with r 1 1,2,3. 15. between the two amplifiers, common connections are made to the reset gates ( 1 r), reset drains (rd) and output gates (og). 16. an external load is required for each output amplifier. for the hr amplifier, this can be a resistor of about 5 k o (non-critical) or a constant current type of about 5 ma. for the ls amplifier, the load should be either 3.3 k o or 7.5 ma. the on-chip amplifier power dissipation is approximately 30 mw for the hr amplifier and 50 mw for the ls amplifier. # e2v technologies 100013, page 7 maximum voltages between pairs of pins: pin connection pin connection min (v) max (v) 15 osh 11 odh 7 15 +15 16 osl 13 odl 7 15 +15 19 r 1 2hv 18 r 1 dc 7 20 +50 19 r 1 2hv 27 r 1 3 7 20 +50 output transistor current (ma) 20
drive pulse waveform specification the device is of a 4-phase construction, designed to operate in 2-phase inverted mode. this is achieved by applying common timings to phases 1 1 and 1 2, and phases 1 3 and 1 4 of the image and store sections. suggested timing diagrams are shown in figs. 4 C 11. the following are suggested pulse rise and fall times. clock pulse typical rise time t (ns) typical fall time t (ns) typical pulse overlap i 1 140 5t5 200 140 5t5 200 @90% points s 1 140 5t5 200 140 5t5 200 @90% points r 1 1 10 10 @70% points r 1 2 10 10 @70% points r 1 3 10 10 @70% points r 1 2hv 25 25 see note 18 r 1 2hv sine sine sinusoid- high on falling edge of r 1 1 notes 17. register clock pulses are as shown in figs. 5 and 6. 18. an example clocking scheme is shown in fig. 5. r 1 2hv can also be operated with a normal clock pulse, as shown in fig. 6. the requirement for successful clocking is that r 1 2hv reaches its maximum amplitude before r 1 1 goes low. electrical interface characteristics electrode capacitances at mid clock levels connection capacitance to ss inter-phase capacitances total capacitance units i 1 1 2.4 2.4 7.2 nf i 1 2 5.4 2.4 10.2 nf i 1 3 2.4 2.4 7.2 nf i 1 4 5.4 2.4 10.2 nf s 1 1 2.4 2.4 7.2 nf s 1 2 5.4 2.4 10.2 nf s 1 3 2.4 2.4 7.2 nf s 1 4 5.4 2.4 10.2 nf r 1 1 68 98 166 pf r 1 2 56 68 124 pf r 1 3 89 74 163 pf r 1 2hv 15 18 33 pf series resistances connection approximate total series resistance i 1 116 o i 1 214 o i 1 316 o i 1 414 o s 1 116 o s 1 214 o s 1 316 o s 1 414 o r 1 16 o r 1 26 o r 1 36 o r 1 2hv 8 o approximate output impedance large signal amplifier 350 o high responsivity amplifier 400 o 100013, page 8 # e2v technologies
1 1 1 2 1 3 1 4 8184a pulse timings and overlaps figure 4: clocking scheme for 2-phase inverted mode operation # e2v technologies 100013, page 9
r 1 2hv r 1 1 r 1 2 r 1 3 8237 figure 5: clocking scheme for multiplication gain (sine wave clocking scheme) (see note 19) figure 6: clocking scheme for multiplication gain (conventional clocking scheme) (see note 19) note 19. to operate through the osh output amplifier, the r 1 1 and r 1 2 waveforms should be interchanged. 100013, page 10 # e2v technologies r 1 2hv r 1 1 r 1 2 r 1 3 8238
1 r r 1 3 t 1 t w t 2 8055 figure 7: reset pulse t w = 10 ns typical t 1 = output valid t 2 4 0ns figure 8: pulse and output timing # e2v technologies 100013, page 11 r 1 3 1 r os reset feedthrough signal output vos 8069
i 1 1=i 1 2 i 1 3=i 1 4 s 1 1=s 1 2 s 1 3=s 1 4 r 1 1 r 1 2 r 1 3 r 1 2hv 1 r line transfer: 1037 cycles transfer from store to register and readout frame transfer: 1032 cycles integration period extended first pulse at start of frame transfer 4 10 m styp. 8280 figure 9: example frame timing diagram figure 10: example line timing diagram (operation through osl, see notes 19 and 22) 100013, page 12 # e2v technologies i 1 1=i 1 2 i 1 3=i 1 4 s 1 1=s 1 2 s 1 3=s 1 4 r 1 1 r 1 2 r 1 3 r 1 2hv readout: 1072 cycles 4 1 m s 4 1 m s line transfer period 8281
r 1 1 r 1 2 r 1 3 dg s 1 1 s 1 2 s 1 3 s 1 4 n line transfer cycles 4 10 m s 4 1 m s 4 0.5 m s 8187 figure 11: operation of the dump gate to dump n lines of unwanted data from the standard register note 20. wanted lines of data must be completely read out before dumping unwanted data. figure 12: output circuit schematic (osl and osh amplifiers) note 21. the amplifiers have a dc restoration circuit that is internally activated whenever s 1 4 is high. # e2v technologies 100013, page 13 og rd 1 r s 1 4 (internal connection) od substrate ss 0 v output external load os r 1 3 r 1 2 r 1 1 c n 8188
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 abd ss i 1 4 i 1 3 s 1 4 s 1 2 ss ss dg og odh rd odl ss osh osl 1 r r 1 dc r 1 2hv dg ss dd r 1 3 r 1 1 r 1 2 ss s 1 3 s 1 1 i 1 1 i 1 2 ss ig image section 1024 active columns +32 dark reference 1024 active rows 13 m m square elements 5 dark reference rows 2 transition rows store section total 1056(h) x 1037(v) elements 13 m m square 1056 register elements 604 multiplication elements 468 standard and corner elements 16 overscan elements 16 overscan elements 1 transition row 8297 figure 13: schematic chip diagram figure 14: line output format (for example line timing figure 10) note 22. there is a 1-line propagation delay between transferring a line from the store section to the standard register and reading it out through the osl output amplifier. 100013, page 14 # e2v technologies 16 overscan 15 dark reference 1024 active outputs 15 dark reference 8283 ** * = partially shielded transition elements
c image centre see note x a f e h k pitch d image plane b k pitch 36 pins 1 g j pin 1 marker 1 36 14 13 23 24 8298 figure 15: package outline outline note the image centre is aligned centrally in the package in direction x, to within a tolerance of + 0.2 mm. ref millimetres a 37.40 + 0.37 b 26.50 + 0.27 c 9.93 + 0.25 d 1.68 + 0.25 e 3.0 + 0.3 f 5.0 + 0.25 g 0.46 + 0.05 h 22.86 + 0.23 j 33.02 + 0.33 k 2.54 + 0.13 printed in england # e2v technologies 100013, page 15 whilst e2v technologies has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences o f any use thereof and also reserves the right to change the specification of goods without notice. e2v technologies accepts no liability beyond that set out in i ts standard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information cont ained herein.

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